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FET Support (English) => Get Help => Topic started by: math on July 15, 2024, 04:13:37 PM

Title: Getting information about schedule generation interna
Post by: math on July 15, 2024, 04:13:37 PM
Hi!

When generating a new schedule, FET tries to add all activities to the schedule such that all constraints are fulfilled. When adding an activity results in a violation of contraints, a different placement of activities gets evaluated until (hopefully) finally a valid solution is found.

Is it possible to enable some kind of logging of this placement process? Is it perhaps possible to get an information which constraint has been violated during the scheduling process?

Regards, Matthias
Title: Re: Getting information about schedule generation interna
Post by: Liviu Lalescu on July 15, 2024, 05:54:41 PM
Hello, Matthias,

When you hit Generate, FET sorts the activities, 1, ..., n, where 1 is the most difficult and n the easiest, according to some objective but not perfect estimations.

FET places 1, 2, ..., i. There might be constraints broken, but FET will swap the activities recursively to make place for say 4th. But if it cannot place directly or by level>=1 swap to place i+1, FET chooses a slot and displaces all activities of that slot and places i+1. This is a level 0 swap. It is possible to show, for each time slots of the week, the first constraint which makes i+1 impossible to place at level 0.

Am I clear to this point?

So, it is possible to show at each step say 5*6 slots (5 days per week, 6 hours per day) and activity id and the first broken constraint. Some work is needed to add in each constraint type this logging. Not too difficult work. Hmm... I was just going to say "not too useful", but might be useful to log this information when FET reaches a new highest stage.

I think I will add this in the TODO.